Basic digital design Verilog Python Digital verification concepts
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
Difference between virtual sequencer & virtual sequence.
1. UVM phases and which is task and which is function
Basics of Networking. programming . Projects
Write a verilog code to design synchronous counter using verilog
Mostly related to VLSI domain.
Data Structures questions Bit allocation questions Stack and heap design questions.
How do you handle stress?
Write C code for Fibonacci series using recursion. Write c code for swapping 2 nos without using any other variables.
Basics of verilog and sv
Viewing 2001 - 2010 interview questions