Introduce yourself. Asked to write code for clock generator (verilog) And also in contraintns ( SV)
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
It is the final round. Here they asked about family members and occupation.About my schoolings. How did you perform in your 1 and 2 round, which is best of you. What do you know about SMARTDV. Which domain are you interested in. Is it ok about the commitment and bangalore. Atlast any questions for HR. THANK
1. Sv, uvm environment question 2. Coding of UVM architecture 3. Digital electronic 4. AMBA protocol
Why did you choose Texas Oncology?
FIFO coverage implementation in sv
D flip flop and its working and basic gate coding's
Why do you want to switch to automation instead of development?
Have you use Polarion, DOORS management tools? Do you know Python? Are you fimilar with ARP4754A, DO-178C?
They asked Digital questions, verilog
Basic questions on Digital electronics and C programming.
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