Basics of digital,. VLSI design etc
Design Verification Engineer Interview Questions
3,714 design verification engineer interview questions shared by candidates
What is a hash table?
What is latency and throughput?
Basics of sv, sva, verilog
My experience was bad in 2 rounds otherwise good in other 3 rounds.
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
C++ encapsulation, inheritance and polymorphism
Nothing was unexpected, very minimal behavioral questions. All the technical questions are regarding to computer architecture subjects.
ask the concept of virtual function, pure function in c++. Ask previous verification experience. An question about how to write a c program to judge whether a machine is big-endian or little-endian
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