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MESI Protocol FIFO Verilog and condition for full and empty Build FSM for 20 story building elevator (you have control in elevator and controls on every floor and discuss what floors take priority Build a clock divider to take 2MHz signal to 1MHz Build a 4:1 MUX using behavioral verilog than structural verilog Tell me how many bits per tag, offset, and addr based on cache structure (1MB 8 way associative) Tell me 5 stage pipeline Tell me about different hazards and explain types of data hazards how would you go beyond 5 stage pipeline
avatar

Verification Engineer

Interviewed at Intel Corporation

3.9★
May 11, 2026

MESI Protocol FIFO Verilog and condition for full and empty Build FSM for 20 story building elevator (you have control in elevator and controls on every floor and discuss what floors take priority Build a clock divider to take 2MHz signal to 1MHz Build a 4:1 MUX using behavioral verilog than structural verilog Tell me how many bits per tag, offset, and addr based on cache structure (1MB 8 way associative) Tell me 5 stage pipeline Tell me about different hazards and explain types of data hazards how would you go beyond 5 stage pipeline

1. Few questions on writing constraints for certain scenarios. 2. FSM for number divisible by 3 3. UVM subscriber, sequences, TLM ports and FIFO. 4. write code for random number generation for given distribution and ranges. 5. byte addressing in an integer memory system. 6. constrain for non-overlapping segment-addresses generation. 7. Explain any testbench architecture you have worked on. 8. Lots of simple questions to test SystemVerilog and OOP concepts.
avatar

SoC Verification Engineer

Interviewed at Apple

4.1★
Mar 23, 2017

1. Few questions on writing constraints for certain scenarios. 2. FSM for number divisible by 3 3. UVM subscriber, sequences, TLM ports and FIFO. 4. write code for random number generation for given distribution and ranges. 5. byte addressing in an integer memory system. 6. constrain for non-overlapping segment-addresses generation. 7. Explain any testbench architecture you have worked on. 8. Lots of simple questions to test SystemVerilog and OOP concepts.

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