Basics of sv, sva, verilog
Design Verification Engineer Interview Questions
3,714 design verification engineer interview questions shared by candidates
It was a quetion about linked lists.
It was a quetion about pysical memroy.
ask the concept of virtual function, pure function in c++. Ask previous verification experience. An question about how to write a c program to judge whether a machine is big-endian or little-endian
questions about OVM process
Computer Architecture, Logic Puzzles, SystemVerilog, C, Algorithms,Assembly
Virtual functions, forks, verification basics, OOPs principle
Find the number of '5''s in a rolling window of size 10. Flag an error when the count>4
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
No difficult question. Only job shadowing did not really mean job shadowing!
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