1. The interview showed a complex SVA and asked me to explain the functionality of the assertion. 2. A C function which reads the value from a specific address. 3. A question about Functional coverage 4. Questions about coverage (code and functional) 5. UVM factory, config_db, 6. Formal verification 7. Processor based verification. Basically they were asking how you verify a Subsystem using C/C++ 8. AHB-AXI bus
Design Verification Engineer Interview Questions
3,723 design verification engineer interview questions shared by candidates
Basic Questions; What are your greatest strengths?
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
How my experience is related to the job description.
The interviewer was from a different background, hence there wasn't any question-answer session
Explain what you learned in this course (VHDL, design classes, object oriented programming, etc)
Do not want to give it away but learn computer architecture well
Questions on computer architecture, bitwise C, exercise on HDL/C/pseudocode for an FSM, logical circuits There was an emphasis on describing my thought process for my solutions rather than their actual results.
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