What do you like to do in your free time?(yeah)
Design Verification Engineer Interview Questions
3,723 design verification engineer interview questions shared by candidates
Logical and analytical question. Test will be taken on hackerrank.
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
paging, hypervisior,
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
Various Verilog detailed questions. I had about 3 months experience of Verilog some 8 years ago. I can't remember the details of the questions.
Basic Questions; What are your greatest strengths?
Explain what you learned in this course (VHDL, design classes, object oriented programming, etc)
Few logic and design based questions, Asked given n number of bits for address bus how much memory can be accessed
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