SV, V, UVM, Problem solving, Advanced formal verification based questions, experience based questions
Design Verification Engineer Interview Questions
3,723 design verification engineer interview questions shared by candidates
Questions on computer architecture, bitwise C, exercise on HDL/C/pseudocode for an FSM, logical circuits There was an emphasis on describing my thought process for my solutions rather than their actual results.
Most of the things were on ARM architecture, AMBA protocols, SV and UVM, Design concepts and Analytical skills
Microprocessor Interrupts C programming ARM architecture Amba
The interviewer was from a different background, hence there wasn't any question-answer session
Verilog code for basic circuits
There was no tehnical interview for no experience engineer
Based in UVM and System verilog and project related questions
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
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