if I talk to your previous boss, what he/she/they gonna say about you?
Verification Engineer Interview Questions
3,720 verification engineer interview questions shared by candidates
model ADC in verilog, how to find frequency of a signal in verilog
Write the verilog code for D flip flop?
Write top level test bench that sets up he virtual interface
What are your goals personally and professionally?
C++ question about returning the amount of bits in a certain value.
C++, SystemVerilog basics
how to impliment A=7.5B w/o using *, /
Some question related to accessing analysis ports in a sequence ( via sequencer)
Basic computer architecture questions, pipeline concepts and hazards. FSM for a sequence detector. Fibonacci using recursion and linked list reversal. Some scripting question which i could not answer.
Viewing 2921 - 2930 interview questions