I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Verification Engineer Interview Questions
3,720 verification engineer interview questions shared by candidates
OOPs questions and also ASIC and Verfication based questions
Is program counter a physical memory address or a virtual address?
How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
Why Qualcomm?
question around the system verilog ,verification methodology.
System Verilog Virtual functions
System Verilog ,UVM Basics, Questions on Resume. Assertions,Constraints. Memory Verification plan
Constraint for 8-bit opcode (SystemVerilog) ➤ Only one bit can be set in the 8-bit opcode (i.e., one-hot encoding). Matrix size based on opcode bit index ➤ Based on which bit is set in the 8-bit opcode, generate a square 2D array (e.g., if bit 4 is set, matrix is 4x4).
Constraint randomization based question linking to AXI and memory filling
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