1. Given a common gate transistor with a capacitor between source and gate , and drain terminal grounded , calculate the impedance seen by ac signal from source . 2. Given an OP-AMP circuit and to find output voltage , which involves KCL type solving PS: The interviewer is calm and friendly - He was telling that he visited 4 campuses including one IIT- M -- where he didn't find good talent from UG , PG from there as well . So, you might now , of what standard he is expecting . This interviewer is my eye opener . To be a successful Analog engineer, you may require a lifetime !!!!
Senior Rf Analog Design Engineer Interview Questions
28 senior rf analog design engineer interview questions shared by candidates
Asked some questions about op-amp trade-offs and miller compensation.
ADC/DAC: ADC selection criteria, explain them, linearity, staircase waveform
They care more about ADC knowledge. Although the job title is RF design, the manager asked many ADC and mixed signal questions.
RLC network. Finding output impedance of a given circuit. Solving a transfer function for a closed loop circuit.
Q: If you could work on any research project you wanted, what would it be?
What is sensitivity list?
Nothing too difficult, I was mostly asked about group projects I've worked on and a few questions regarding Smith Charts and inductors.
What measures did you take to improve timing of your design (a cadence virtuoso design project)?
Most of the questions were based on my resume
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