Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.
Given this basic design interface, what things would you verify?
What is your experience with random constrained stimulus?
This was an entry level position. Basic questions were asked about FIFOs and metastability. Then I was asked to code an RTL Design for an Ethernet cable. Had to dissect packets of data and extract the payload while discarding everything else.
1. 30 mins phone screening about my resume and my background. 2. a) fill out a truth table for 4 to 1 mux. b) implement an 8 to 1 mux with 3 given 4 to 1 mux. c) 1)Given few declared variables in a struct C/C++, calculates the total number of bits that allocate and occupy in the memory. EX. ..... char hello; uint_32 hi[5];....... ANS: total bits of memory require = 8 + 32 * 5 = 168 bits. 2) Imagine that an HDL code is sending 168 bits of data to the two variables in struct C/C++. Fill out the bit length of each variable. ANS: hello[7:0] and hi[167:8]. Very easy questions.
Logic Design Questions
They asked me 1)about the various concepts of verifying a design and also provided me scenarios as to how we can verify them . 2)to explain my previous projects and my responsibilities for each of the projects . 3)Also, the software team asked me a programming example. There were various teams of people wanting me to explain my previous job profile and responsibilities and explaining me about their company culture. Overall, It was a very good experience for me since I was fascinated by the fact that my job profile and trading can coincide !! and how!
What classes did you like/dislike?
Do you know object-oriented code?
A question on FIFO depth and Constrained Random Verification
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