setup/hold time violation
Fpga Verification Engineer Interview Questions
35 fpga verification engineer interview questions shared by candidates
Software Testing skills-Finding bugs in a calculator application
Basic hardware questions and what happens when sampling during the rising edge of the clock
Technical
Systemverilog, UVM related questions + a presentation related your work.
Which one do you like more: designing, simulating, or testing?
Questions about pointers and file usage.
Where do you see yourself in the future? (technical, leading, or managing)
Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.
what are the stages in fpga verification
Viewing 11 - 20 interview questions
See Interview Questions for Similar Jobs
Asic Verification EngineerFpga EngineerCpu Verification EngineerFpga Hardware Design EngineerDesign VerificationVerificationSenior Verification EngineerDesign Verification EngineerFpga Design EngineerAsic Design Verification EngineerCpu Verificatie EngineerVerification EngineerSenior Asic Verification EngineerVerification ManagerVlsi Design EngineerDigital Verification EngineerSenior Vlsi Design EngineerVerificatie Design Engineer