On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
setup/hold time ;verification coverages and types
General resume questions
Q1. FIFO depth, given read and write rates for a burst of x writes Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms) Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms) Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms) Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms) Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
How to implement a priority encoder in Verilog?
Describes one of your projects
Sv and UVM project knowledge protocol mentioned in CV
FSM, SystermVerilog, and software leetcode related questions.
Simple questions like what you know about employment Verification. How you came to know about it etc.
Q. Describe your test plan for a FIFO
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