What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
loop stability calculation, dominant pole
Clock domain crossings and reset domain crossings
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
What is your experience with random constrained stimulus?
about DV methodologies, DV techniques, protocols
digital, verilog, system verilog
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
Tell any 5 commands and how to validate floorplan
Viewing 901 - 910 interview questions