1. Circuit Design 2. Physical Design 3. Scripting
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
Know the details of your past work experience.
How is uncertainty determined.
what the keyword volatile means in C
Basic Digital Circuit and Analog Circuit Questions
All kinds of fork joins
they ask the inputs into the tools for different steps of physical design.
How do you access a private variable in a public class from another class in java.
Draw the circuit base on the coding provided
Screening: Setup and Hold time violations Synthesis constraints (ideal path, false path) Open page and closed page policy DDR project in-depth Panel round: Round 1 Asynchronous FIFO: How to design and problems faced? Synchronous FIFO verilog code Round 2 What is a glitch? When can it occur? Explain with waveforms. How to resolve the problem of glitches? How to design glitch-free circuits Static and dynamic power, Ways to reduce both Given a list in Python Sort it without using sort() Setup and hold time constraints Round 3 Resume projects and experience Open page vs closed page policy What is pipelining Adding pipeline registers to the timing path: It’s impact on performance and area Round 4 Verilog code for a given problem: given x config(7), y config(6) Convert into corresponding x and y coordinates and trace the path (Can be done using fsm for tracing both x and y coordinates) Round 5 Verilog coding (Question related to rotating bits for a given number) Most challenging problem faced Round 6 Verilog arbiter code (3 requests), can store outstanding requests in fifo
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