What is Setup and hold time
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
2. some binary arithmetic.
gate level, digital circuit like counter, power problems
Moderate, no unexpected questions asked.
What will gm change if we enlarge the W/L of a transistor by 2. Compare the gm of a BJT and MOS device. Slew rate problem
write a verilog code of moving average
min and max timing violation
You are given 2 receiver antennae and one transmitter antenna. Describe what happens to the received signal when changing the distance between receivers (close and far apart).
Write the verilog of ROB on a paper.
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