Given read and write freq, how to calculate FIFO depth?
Verification Manager Interview Questions
3,714 verification manager interview questions shared by candidates
Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
Draw a NAND using cmos gates
system verilog constraints interview questions
tlm and its benefits. difference between blocking and nonblocking transactions
detailed test plan for a synchronous fifo
Basic CMOS Physical design related Sta Tool related
- about SV, FIFO design, arbiter design
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