A lot of technical questions relating to logic design, timing and IC design. Also a lot of questions about what I had worked on in the past.
Verification Manager Interview Questions
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not many hard questions. hardest had to be "how are you at work?"... very open ended question. they seemed to want me to either really praise myself or really berate myself
Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
Nothing of that sort
not much difficult
Mostly SV and methodology based and also previous projects.
Write the VHDL or Verilog code for a given state machine diagram.
One of them asked about very fundamental elementary questions which was hard to recollect
There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like always @(posedge clk, reset_active) begin if(reset_active) do somthing else do something end vs: always @(posedge clk, reset_active) begin if(!reset_active) do something else do something end What is the difference in above two impl's.
A basic testplan scenario
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