One hour phone interview. asked basic questions on OOPs concepts, system verilog, FSM, latches.
Verification Manager Interview Questions
3,721 verification manager interview questions shared by candidates
Find 5 first maximums of an array under the condition than if two numbers are sitting side by side in the array, one of them cannot be in the maximum list.
Q : Draw the FSM diagram for a given case considering mealey machine and taking the overlap cases.
mentioned above in detail .. ..
1. basics of Verilog. 2. verification coding questions. 3. coding question in Verilog.
What assertions did I write to verify functionality of my SV projects? Sequence detector 10110? What is FSM-D?
What is carrier aggregation,MIMO, OFDM , RACH procedure. What is the difference between enum and a macro difference between struct and union difference between interface and abstract class and be through with every line on your resume.
Fully explain what kind of projects have you done.
Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.
Output the sum of the largest series of consecutive values, in an infinite arbitrary series of numbers.
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