How to make nor gate using two input mux
Verification Manager Interview Questions
3,721 verification manager interview questions shared by candidates
Draw the truth table for a NAND gate.
What are your career goals? Where do you see yourself in five years?
Describe what tests need to be done on memory
NA
CMOS/VLSI, timing, logic on transistor level, Verilog question
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Difference between latch and flip flop, Sequence detector design, Divide by n circuits for different values of n. Few scenarios of assertions, Verilog code for positive edge detector and negative edge detector, Setup and Hold time and few codes to debug and provide output. basic questions in digital on mux, questions on code synthesizing
UVM, SystemVerilog and PCIe protocol
write a program
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