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Verification Interview Questions
3,720 verification interview questions shared by candidates
Logic question to verify the design How would you verify 3 blocks with incorrect label ? suppose one with apple 2 with orange 3 with apple & orange.
Design FSM for some problems
Write a decimal to hex function in C
System Verilog Assertions.
There's a circuit diagram of two parallel capacitors with different charge voltages, connected by a transistor. What happens to those two voltages when the transistor turns on?
they asked about UVM architecture and classes concept .
explain about your project
Systemverilog, UVM, prime number generation, FSMs
questions on protocols and digital design basics
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