Difference between task and function, inter assignment and intra assignment statement, flipflop and latch, etc
Verification Interview Questions
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What is difference between dynamic and associative array.
UVM, system verilog, C++, puzzles and ethernet related
SystemVerilog, UVM environment, AHB, AXI, Ethernet
What challenges have you faced and how did you overcome them?
Aptitude, C++, Verilog, Digital Design basics and logical reasoning
Using constrained randomization what types of functional coverage would you expect to see on a PCIe bus?
Imagine you and HR manager meet in the elevator. What would you say (within 1 min) to convince him/her to hire you?
A question on FIFO depth and Constrained Random Verification
Written test process Interview Very tough
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