Most of the interview questions were from my resume and projects i have done. Some of the questions were based on VLSI design concepts
Verification Interview Questions
3,722 verification interview questions shared by candidates
About me, school projects and all content in CV. Communication protocols and signal analysis Algoriths known
Setup and Hold Time Violations
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
about projects, verification methodologies, UVM, System Verilog testbench, Computer Arch, MESI protocol, Cache UVM testbench components, constructs Digital Design questions FSM types and differences Divided by 2 clock design and code Basic Gate level designs
Tell me about yourselves , Strength and weakness Job expectations
Programming, queries, test cases, aptitude
Questions about debug of failure
How to determine cache size using a C program?
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