At one point, I was asked if I would go to the customer in Texas. It sounded to me like the interviewer was talking about a single trip. I should have asked how much time I would spend in Texas. Later, when the offer came, they wanted me to spend one week out of every month in Texas.
Verification Engineer Interview Questions
3,715 verification engineer interview questions shared by candidates
Linux mount filesystem
Diffcult
it was general discussion about logic design and he gave me discribtion about circuit and asked me to leocate the signals that i should select for testing and verifying they gave me small task about an alu and i am supposed to write verification code in system verilog for it , actually they were very generous they provide the matrials to learn more about system verilog and how to write such a design
Coding questions were on Constraints and Assertions.
Iq questions
Tell me your personal advantages and disadvantages.
Tell about yourself, experience of previous employment and certifications ?
Unexpected question was string manipulation using C++. Since I have not used C++ for strings since I have started working and it is not a hands-on question that has anything to do with the technical expertise of the person, it was kind of unexpected.
SystemVerilog basics and UVM basics
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