Build a stack component using a simple memory component
Verification Engineer Interview Questions
3,720 verification engineer interview questions shared by candidates
Not a behavrioal interview, pure coding interview
I was asked on basics of SV,UVM and computer architecture
Tell me about your self
1 Digital Design implementation questions.. ex logic gates design using mux, flipflop vs latch 2. Verilog questions ... always vs initial blocks, blocking vs nonblocking, casex vs casez, timing regions
About the multiplexers in digital electronics
Flipflop and latch difference? Mod5 asynchronous counter circuit
SV and UVM based questions
Explain factory method in UVM
What is config.db in UVM
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