Mainly System verilog and uvm bases questions,Set up time hold time How to generate a skewed clock How to do clock domain crossing Create a sequence generator Sorting based alogorithm Questions
Verification Engineer Interview Questions
3,720 verification engineer interview questions shared by candidates
questions were asked from design point of view
Basic questions about UVM
How to compute perspective correct texture coordinates when rendering a triangle
Timing diagram out put and combinational circuit output
how would you delete an object in SV? what happens when you assign a parent to child? Explain UPF and what we can accomplish using it?
How would you count the number of objects you created for a particular class?
State Machine, Verilog code writing
SV and UVM and the lastest projects
How are you generating clock in verilog, difference between fork-join and begin-end
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