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Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
How do you manage your time?
describe one of ur project
UVM Verilog Verification thinking Logic gates
Digital electronics,vhdl, verilog, system verilog
all basics of SV,UVM and project
They asked me about school projects that I have done.
NVME Project How it works?
Uvm based events, clk generation, how would you verify a given circuit
hardware questions like division by 3 FSM, linked list, c function and you should say what is the output, how you'd solve concurrency of 2 cpu trying to change same register value
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