Uvm related Project related Sv concepts Fifo full empty conditions Fork join concepts Axi ahb difference
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
Design an FSM and write Verilog code for an asynchronous fifo
Questions about debug of failure
uvm basic, ovm basic and python
Most of the interview questions were from my resume and projects i have done. Some of the questions were based on VLSI design concepts
Difficult technical questions, very unforgiving when I got one question wrong, they ended the interview straight away after that.
power integrity understanding: including impedance threshold define and theory.
What is the difference between task and function
Write a Scoreboard for verifying the average of 5 previous values, where the data is coming sequentially, I.e 1 value at every posedge of clk.
polymorphism in system verilog and virtaul interfaces.
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