about UVM, explain project (it was on UVM) , basic object oriented concepts like abstraction, constructor, function overloading
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
HR interview were standard questions. Interview with manager were more technical and based on testing and previous experiences
Computer Architecture, Logic design, validation, software, behavioral.
1. about previous experirnce
All basics of System Verilog
Not really difficult, jut really technical
What is the purpose of a capacitor and why would you want to have one or multiple on a circuit.
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
Was tested on computer architecture, pipeline, hazards, fsm, uvm basics, writing system verilog test benches for resume projects
find the minimal number of semi-binary numbers that sum up to a given number. semi-binary is an integer that is composed only by the digits 1 and 0.
Viewing 1871 - 1880 interview questions