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Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
What is the reason you go for a PVT on SoC and what is the criteria you need to consider for validating the SoC
Introduce your school projects
basic setup hold time
What is synchronous and asynchronous reset? Setup time and hold time
System verilog and UVM
Intraduse About project Verilog code
Given waveform of input signals and combinational and sequential circuit and question was to draw wave of output signal.
Uvm, system verilog
Describe a stressful situation at work and how you handle it.
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