Software Testing skills-Finding bugs in a calculator application
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
Basic hardware questions and what happens when sampling during the rising edge of the clock
1. Build a circuit to ti produce a signal high whenever output changes also asked this to be implemented in terms of FSM suitable for RTL CODING. Asked about data dependencies and control dependencies, caches types and cache replacement policies. What is virtual fiction in c++ and recursive functions code in c Mostly basics
Why do you want to work for Landing?
digital electronics paricularly in sequential..
write a complete AXI packet class in UVM
basic resume, metastability, race condition, how classes are destroyed in SV?, basic object oriented concepts.
- timing questions: setup, hold, slack, critical path, max frequency, what is STA, how to improve the timing, etc
Q: Number of test vectors for a priority encoder with "n" inputs.
Q: FSM for detecting a particular sequence.
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