Can we override constraints like data members?
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
Why do we need a virtual interface?
Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
technical questions which are related to projects you have done
c++ basics - virtual functions, function vs task difference, coverage , constraints
write assertions for the given timing diagram
SV, UVM, Driver sequencer handshake mechanism
Verilog code for basic circuits
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