first was an assembly question, to implement multiplication with certain commands and few registers avaliable. second question was to build a xor gate with 4 wierd components which are sometimes Z and sometimes have output.
Verification Engineer Interview Questions
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1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
show how to access an address in cache and implement it.
Had to write a verilog code for some handshaking protocol.
Digital questions, UVM environment based questions
How to use muxes to implement an XOR gate?
Delayed assignment and delayed evaluation in Verilog
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
Resume questions, fifo questions, assertions, coverage
General questions in Python, C, Verilog, and SystemVerilog.
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