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Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
Asked about coursework. Asked me to talk about the principles of object oriented programming. Asked me to walk through a simple coding problem involving strings. Asked a simple logic design question involving muxes.
In SystemVerilog: Write the code for stepping through a circular array. Also, how would you initialize a multi-dimensional array?
how would you code an adder in verilog
Talk about yourself andyour education
Various Verilog detailed questions. I had about 3 months experience of Verilog some 8 years ago. I can't remember the details of the questions.
Few logic and design based questions, Asked given n number of bits for address bus how much memory can be accessed
How will you verify MOESI protocol on a cache line to see if it transitions to all possible states with minimum number of access
1. The interview showed a complex SVA and asked me to explain the functionality of the assertion. 2. A C function which reads the value from a specific address. 3. A question about Functional coverage 4. Questions about coverage (code and functional) 5. UVM factory, config_db, 6. Formal verification 7. Processor based verification. Basically they were asking how you verify a Subsystem using C/C++ 8. AHB-AXI bus
Interview process had 5 technical rounds including question on puzzles , mathematical derivation related logic, permutation and combination questions mostly , logical questions to derive at particular answer. 1. get 4 ltr out of 3 ltr and 5 ltr jar 2. combination question 3. few question relating to infrastructure as code
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