-------Intel,MA.-------------------- 1.Intro about the project and what they are doing currently. 2. Overview of my education and prof skills 3. He stopped before the project, Being an verification engineer he found some bugs in my resume. 4.Moving on, He asked me about the projects and dived deep into it. Design Spec, Test plan, architecture integration. 5. I worked on a RTL project - he asked me to verify it. 6. Testbench setup and the how you verify it. 7. UVM testbench setup. 8. What is reference model and how you use it. 9. In Intel, They used rule based verification. Which I didn't know. He explained why? 10. Trust me I was exhausted at this point. He moved to python to test my coding abilities. 11. I told about my work experience in python and then he said I am not good at python. Ok. 12. The Hustle continues, Computer Architecture - Stages of pipeline. 13. What happens in stall situation in a pipeline. 14. Do we need branch predictor? 15. Types of Hazards 16. Why is coherency required ? 17. What is bus ? 18. What is Exclusive state? 19. What happens when you move from E -> M state? 20. What if two processors try to write the same cache location? 21. If there 4 processor and 4 caches- If P0 & P1 have a S location value, If the P4 trys to write that Location. What will happen? The time is up, He asked you have any question for me....
