They were looking for technical architect for webRtc project. Its porting and optimization of video codecs on TI multicore platform. Its for media resource function hardware. 1. What are error resilience tools available for h.264 video codec. 2. How would you configure video codec for surveillance vs broadcasting scenario? 3. What is cache coherence. 4. How do you make sure that during multichannel video codec operation, data swap in and swap out is minimized? 5. What all resources (memory, DMA channels, cpu time slice etc) needed to port video codec onto target processor? Like what all categories of memory needed? (scratch memory vs persistent memory) ...
