Tell me about a time when you received good customer service.
Senior Verification Engineer Interview Questions
3,721 senior verification engineer interview questions shared by candidates
Logic question to verify the design How would you verify 3 blocks with incorrect label ? suppose one with apple 2 with orange 3 with apple & orange.
Design FSM for some problems
Write a decimal to hex function in C
System Verilog Assertions.
There's a circuit diagram of two parallel capacitors with different charge voltages, connected by a transistor. What happens to those two voltages when the transistor turns on?
they asked about UVM architecture and classes concept .
explain about your project
Systemverilog, UVM, prime number generation, FSMs
questions on protocols and digital design basics
Viewing 751 - 760 interview questions