Question on Project, tool awareness, uvm methodology, driver code and testplan development.
Senior Verification Engineer Interview Questions
3,715 senior verification engineer interview questions shared by candidates
About a time I stood up to authority. One of my top favorite interview questions of all time.
What is the challenge you face when you start a New job?
They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
Tell us about a time that you failed and how did you overcome?
Verification of a processor core - caches/interrupt etc
Draw a block diagram of a simple processor and explain how a particular instruction will flow through it.
How we can integrate agents without them generating stimulus
Some verification related questions were asked?
UVM Concepts and Work Experience of previous project
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