How will you initiate a verification?
Senior Verification Engineer Interview Questions
3,715 senior verification engineer interview questions shared by candidates
Basics and some basic circuit verification
Assertions,SV OOPS, Comp Arch
UVM and verification questions mainly
During the interview, I was asked questions related to my experiences in the field. Setup hold, clock multiple. Specifically, discussions centered around the technical aspects of clock multiple, as well as an exploration of my work experiences and the responsibilities associated with my role.
Explain Timing Diagram in VLSI
1) Tell me about yourself 2) Tell me about the projects on your resume
-General digital flow design -General UVM verification questions
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
General discussion on my coding background and course work
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