Phone Interview with a Design Verification Engineer: Questions on Digital Signal Processing, Analog basics and System Verilog basics.
Senior Verification Engineer Interview Questions
3,720 senior verification engineer interview questions shared by candidates
What have you done since you've graduated?
effective way of an array sorting?
Implement a memory allocation management
Asked some questions on C++, constraints, and basic UVM
basics on UVM and SV
Linked lists, pointers, arrays, registers, and more.
Questions were on digital design, FSM, waveform analysis, verilog coding with inter and intra delays, SVA, test bench scenario writing, CPU vs GPU and pipelining.
The hour-long interview was mostly about the current projects.
write a function that will change variables a<->b without "*", "+", "\", "-"
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