digital, sv, uvm, verilog, scripting basics
Senior Verification Engineer Interview Questions
3,720 senior verification engineer interview questions shared by candidates
set up time, hold time
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
I was asked about basic C++ knowledge, such as encapsulation and polymorphism. I was also asked to interpret some assembly code. A design manager asked me conceptual questions about computer systems and architecture, such as cache and virtual memory.
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
FIFO depth, and ASYNC FIFO test plan
pseudocode for factorial and think of cases that would fail it, they had given me a scenario and to assess it. A design was given and was asked to identify bugs in it.
como voce se ve daqui 19 anos
qustions asked in written test are based on the following topics 1.design of FSM 2. STA 3.design of some logic functions and reduction of logic functions face to face in interview are the questions given in the written test.
describe a project you worked on..
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