They asked what experience I had and what would I do for basic claims submission.
Senior Verification Engineer Interview Questions
3,722 senior verification engineer interview questions shared by candidates
SEL Value; questions about my background; verification process.
What type of skills do you have or want to learn?
4-5 general hdl design questions, fast paced
Draw diagram of jtag logic. Can you use a tdr instead of ijtag?
Two leetcode style questions on arrays, asked to find the output of a SV code and writing Driver class for an SPI with single master and multiple slave.
This was an entry level position. Basic questions were asked about FIFOs and metastability. Then I was asked to code an RTL Design for an Ethernet cable. Had to dissect packets of data and extract the payload while discarding everything else.
It takes 30 minutes found question like halfadder , bitwise operation , function call related problems in the verilog
What is your strengh? Tell me about yourself
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