build module that takes a 2-bit state input (the state value is the actual input to the module) from another module, and changes a single bit output value based on which state you transition to next. These states come from a module in 10 MHz clock domain, You want to write out this 1 bit data from your module at 100 MHz ensuring that the output is stable before 80ns has passed after the state change. Clk to q delay less than 1 ns.
Basic question about my previous job and responsibilities.
If this was your system, where would you place a few valves?
Asked about your experience pertaining to the job, and asked what service area you would prefer to work in.
What my future goals were in the organization
Q: Can you tell me a time that you struggled on a class/club project and how you overcame it
What kind of work do you do now?
I was asked to comment a P&ID, in particular a section which represented a flow controller which acted upon a control valve.
Describe your self. Your role in company. Skills. Work with team
How old are you?
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