Design and architect a simple trading system.
Senior Fpga Design Engineer Interview Questions
681 senior fpga design engineer interview questions shared by candidates
Point errors on a piece of C code
I was asked to design a synchronous system that demonstrated a traffic light where there is a condition that the system should be fair and not starving any state.
Implement a C algorithm as a state machine in verilog
Code a 9-pixel averaging filter in Verilog
ALP questions - what was your biggest technical mistake, have you had to disagree with your boss, etc.
3. What are the best Constraints when you want to transmit signals between two FPGAs? Pass through Signals?
Questions asked were related to projects and internship experience
What are the ways to synchronize signals and busses?
What is the mean time between failures for a flip-flop that has asynchronous data input.
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