Discussed C++ Pointers. I was not expecting that topic. Also, Async Fifos, Dynamic Arrays in SV.
Senior Design Verification Engineer Interview Questions
3,721 senior design verification engineer interview questions shared by candidates
digital circuits and verilog , c language
A question about a house with 4 light bulbs
Bjt. Current. Voltage. Electronics etc
Read after write sequence implementation
Given an error message, what could be the issue.
Virtual Methods , Virtual classes and their difference in system verilog
Object overriding and overloading. Callbacks, mailboxes and semaphores
Questions around GPU pipeline and how it works. Command streamer etc
Exaplain about your project and entire data path of RISC V architecture
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