Verilog questions and digital circuit designs
Senior Design Verification Engineer Interview Questions
3,721 senior design verification engineer interview questions shared by candidates
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
FIFO depth, and ASYNC FIFO test plan
pseudocode for factorial and think of cases that would fail it, they had given me a scenario and to assess it. A design was given and was asked to identify bugs in it.
difference between latch and flipflop?
Prepare a testbench. (Write in Verilog on the board)
digital, sv, uvm, verilog, scripting basics
Questions on pipelining
register vs flip-flop
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