Design a synch FIFO. Was asked a simplified version. Was asked to assume depth of FIFO was 4 and width was 32. He was just looking for how and when I'd update the memory buffer and the control logic for the free and avail Was given a verilog module and asked to figure out what it was doing. Noticed that it was a round robin-ish arbiter. Later was asked if there was any case where starvation (live lock) was possible. It became clear as I was working thru the waveforms there was a specific case where the arbiter can starve any of the requests. Then I was asked to fix the code. Also I was asked how would we catch issue like this. I mentioned that Formal Prop Verif tools are the best vehicles to find bugs on such designs
