Discussions on DFT - seemed like the interviewer was looking for the 2 terms i.e., controllability and observability Can scan chains run on functional clk and data pins. Lock up latches usage in DFT Boundary Scan Design and TAP Controller
Senior Design Engineer Interview Questions
1,015 senior design engineer interview questions shared by candidates
Synthesis constraints Timing checks - setup, hold Related discussion - setup from one FF (in fast clk) to next FF (in sync fast clk/2) Hold for the above scenario Clock Gating How to write RTL assertions
7. Majorly on projects done
1. FSM design and comparision of FSM state encoding techniques
Smith chart, impedance matching with lumped elements. Which matching is better from a harmonic point of view. filter types and different filter characteristics.
what is your experience in delivering wireless hardware radio platforms for mass production?
why you change you job.
CDC and digital basics
Nothing out of the ordinary.
General questions about academic background
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