A question they asked was to code a Full Adder in Vivado using the logic equations that you have to derive and then simulate it using a test bench.
Senior Asic Physical Design Engineer Interview Questions
38 senior asic physical design engineer interview questions shared by candidates
2 input NAND gate, which states will have how much leakage power.
What's the purpose of Placement and what do we care about Placement.
what are the impacts of using very tight skew constraints
pd flow and physical verification questions
Tell me abuot your self
Questions regarding library creating and area of the cells in the library
Antenna Effect, latch up
Explain POCV coefficient based calculation for an actual timing report.
VLSI, Device Physics, Cadence, Verilog and C Programming.
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